In general, there are two techniques typically used for operating a computer of an information processing system. In one of the techniques, a single operating system, also referred to hereafter as an OS, is run on a real computer. In the other technique, a plurality of computers are each implemented as a virtual machine also known as a VM or an LPAR in a virtual-machine system. The virtual-machine system comprises a plurality of virtual machines and operating systems running on a single real computer. It should be noted that a real computer is also known as a physical computer.
A mode in which a single OS is running on a real (physical) computer is called a basic mode. A simplified configuration of hardware resources constituting a real computer in the basic mode is shown in FIG. 1. As shown in the figure, hardware resources of a real computer include one or more central processing units (referred to hereafter as CPUs), a single main storage unit (abbreviated hereafter to an MS) common to the CPUs, one or more channel paths (also called CHPS) and devices (also abbreviated to DEVs) connected to each channel path. These hardware resources constituting a real computer are treated as a single resource.
A mode, in which a plurality of LPARs are configured on a single real computer and a plurality of operating systems run thereon, is called an LPAR mode. A simplified configuration of hardware resources constituting a real computer in the LPAR mode is shown in FIG. 2. In general, in order to implement a plurality of LPARs on a single real computer, a system program known as a virtual-machine control program (abbreviated VMCP) is executed on the real computer. The LPARs are generated under the control of the VMCP and an independent OS is considered to run on each of the LPARs.
The VMCP has a function for allowing the hardware resources of the single real computer to be shared among the LPARs. Methods for allowing the hardware resources of the single real computer to be shared among the LPARs include a technique of allocating the hardware resources to the LPARs on a time-sharing basis under the control of the VMCP, a technique of allowing the LPARs to logically share and appear to exclusively occupy the hardware resources and a combination of both of these techniques. A conventional technique of allocating hardware resources of a single real computer to a plurality of LPARs is disclosed in a document such as IBM's publication entitled "Enterprise System/9000 Enterprise System/3090 Processor Resource/System Manager Planning Guide" (GA22-7123-4).
The technique of allocating input/output channels to LPARs introduced in the above publication is considered to be one of those described above. To be more specific, real CHPs are logically shared, allowing exclusive use by each LPAR. With this technique, subchannels of each real CHP are also logically shared, allowing exclusive use by each LPAR as well.
An example of general specifications concerning input/output instructions and input/output processings including the subchannels described in IBM's publication entitled "Enterprise System Architecture/390 Principles of Operation" (SA22-7201-00).
As shown in FIG. 1, the hardware resources of a real computer include two or more CPUs, one MS, two or more CHPs and a plurality of DEVs connected to each CHP.
In the configuration shown in FIG. 2, the hardware resources of the real computer used as the two CPUs are allocated in such a way that the two CPUs are each exclusively allocated to an LPAR. As for the hardware resource of the real computer serving as the common MS, its storage area is logically shared by and exclusively allocated to the two LPARs. Likewise, the hardware resources of the real computer serving as the four CHPs are logically shared by and exclusively allocated to the two LPARs. A group of DEVs connected to each CHP is exclusively allocated to one of the two LPARs in accordance with the exclusive allocation of the CHP to the LPAR. Similarly, a subchannel (referred to hereafter as a SCH) associated with a DEV is exclusively allocated to one of the two LPARs in accordance with the exclusive allocation of the DEV to the LPAR.
To be more specific, hardware resources CPU1, CHP1, CHP2, DEV11 to DEV1n and DEV21 to DEV2n are allocated to a virtual machine LPAR1, one of the two LPARs, whereas hardware resources CPU2, CHP3, CHP4, DEV31 to DEV3n and DEV41 to DEV4n are allocated to a virtual machine LPAR2, the other LPAR, as shown in FIG. 2. Here, the devices DEV11 to DEV1n, DEV21 to DEV2n, DEV31 to DEV3n and DEV41 to DEV4n are each allocated to one or more independent SCHs.
A relation among the LPARs, the CHP groups and the SCH groups is illustrated in FIG. 3. As shown in FIG. 3, each LPAR exclusively uses a CHP group pertaining to the LPAR whereas each CHP uses exclusively a SCH group pertaining to the CHP. As a result, each LPAR exclusively uses SCH groups pertaining to the LPAR.
To be more specific, a virtual machine LPAR 21 exclusively uses channel paths CHP21 and CHP22 pertaining thereto as shown in FIG. 3. The channel path CHP21 exclusively uses subchannels SCH211 to SCH21n pertaining thereto whereas the channel path CHP22 exclusively uses subchannels SCH221 to SCH22n pertaining thereto.
In addition, a virtual machine LPAR22 exclusively uses the channel paths CHP23 and CHP24 pertaining thereto as shown in the figure. The channel path CHP23 exclusively uses the subchannels SCH231 to SCH23n pertaining thereto whereas the channel path CHP24 exclusively uses the subchannels SCH241 to SCH24n pertaining thereto.
Next, an actual relation between the LPARs and the SCH groups is shown in FIG. 4. As shown in the figure, a virtual machine LPAR31 exclusively uses subchannels SCH311 to SCH31n pertaining thereto whereas a virtual machine LPAR32 exclusively uses subchannels SCH321 to SCH32n pertaining thereto.
In addition, the virtual machines LPAR31 and LPAR32 each use a logical input/output interrupt subclass number abbreviated thereafter to the LISC in order to perform control as to whether or not to acknowledge input/output interrupts for their SCH groups. General specifications of the logical input/output interrupt subclass number are described in a document such as the publication cited earlier.
A region ID abbreviated hereafter to an RID is assigned to each of the virtual machines LPAR31 and LPAR32 for use by a SCH group in the control for identifying the LPAR to which the SCH group pertains. The RID is assigned a value unique to the associated LPAR. Since the unique value is also held by all SCHs in the group pertaining to the LPAR, the SCH group holding the RID value can be associated to the LPAR.
For example, the virtual machine LPAR31 shown in FIG. 4 is assigned a LISC value of 1 and a RID value of 1. Accordingly, the SCH group comprising subchannels SCH311 to SCH31n are also assigned the LISC value 1 and the RID value 1. On the other hand, the virtual machine LPAR32 shown in FIG. 4 is assigned a LISC value of 2 and a RID value of 2. Accordingly, the SCH group comprising subchannels SCH321 to SCH32n are also assigned the LISC value 2 and the RID value 2. The virtual machine LPAR31 operates on the real computer with LISC=1 and RID=1 whereas the virtual machine LPAR32 operates on the real computer with LISC=2 and RID=2.
When an LPAR operates on the real computer as a virtual machine, the VMCP sets a logical input/output interrupt subclass mask in a control register, abbreviated hereafter to the LISCM, to the logic value 1 corresponding to the LISC value. General specifications of the logical input/output interrupt subclass mask in a control register are described in a document such as the publication described above.
The format of the LISCM is shown in FIG. 5. As shown, the control register is 32 bits in length. Bits 0 to 7 are used as LISCMs with each bit associated with LISC values 0 to 7. The remaining bits 8 to 31 are not used in this embodiment, but may be used in applications where more than seven LPARs are operational.
With the virtual machine LPAR31 operating on the real computer, the LISC is set to the logic value 1 as described earlier. Accordingly, bit 1 of the LISCM is set to the logic value 1 while bits 2 to 7 are set to the logic value 0. With the virtual machine LPAR32 operating on the real computer, the LISC is set to the value 2. Accordingly, bit 2 of the LISCM is set to the logic value 1 while bit 1 and bits 3 to 7 are set to the logic value 0. Bit 0 of the LISCM is used by the real computer, that is, by the VMCP. This bit is not available for use by the LPARs and is normally set to the logic value 1.
A timechart depicting allocation of the resources of the real computer to the VMCP and the virtual machines LPAR31 and LPAR32 is shown in FIG. 6. The figure shows resource allocation to the virtual machines LPAR31 and LPAR32 operating on the real computer. As shown in the figure, the sources of the real computer are allocated to the VMCP during periods of time 501, 503 and 505. The same resources are allocated to the virtual machines LPAR31 and LPAR32 during periods of time 502 and 504 respectively. During the periods of time 501, 503 and 505, the value of the LISCM expressed in binary format is `10000000`. Only input/output interrupts for input/output instructions issued at LISC=0 are acknowledged. Input/output interrupts for input/output instructions issued at LISC=1 and LISC=2 are, however, pending and held by hardware.
With the virtual machine LPAR31 running during the period of time 502, the value of the LISCM expressed in binary format is `11000000` acknowledging only input/output interrupts for input/output instructions issued at LISC=0 and LISC=1. Input/output interrupts for input/output instructions issued at LISC=2 are, however, pending and held by the hardware.
With the virtual machine LPAR32 running on during the period of time 502, on the other hand, the value of the LISCM expressed in binary format is `10100000` acknowledging only input/output interrupts for input/output instructions issued at LISC=0 and LISC=2. Input/output interrupts for input/output instructions issued at LISC=1 are, however, pending and held by the hardware.
Accordingly, input/output interrupts for LISC=2 occurring during the period of time 502 are held by the hardware and not acknowledged until the period of time 504 in which the virtual machine LPAR32 is dispatched by the VMCP. Likewise, input/output interrupts for LISC=1 occurring during the period of time 504 are thus held by the hardware and not acknowledged until a period in which the virtual machine LPAR31 is dispatched by the VMCP.